IC Validator is a comprehensive and productivity boosting signoff physical
verification solution improving productivity for customers at all process nodes from
mature to advanced. IC Validator offers the industry’s best distributed processing
scalability to over 2000 CPU cores. The tool’s performance and scalability has
enabled some of the industry’s largest reticle limit chips with billions of transistors,
same day design rule checking (DRC), layout versus schematic (LVS), and dummy fill
IC Validator physical verification is seamlessly integrated with Fusion Compiler™ RTL-to-GDSII solution and IC Compiler® II place and route system in the Fusion Design Platform. This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment.
Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. Learn more about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.
Innovations in IC Validator for Advanced Node Physical Signoff
IC Validator DRC in the Cloud: Demo
Explorer DRC: Demo
Learn about latest technologies in IC Validator including; Explorer DRC, Live DRC, Scalability, Elastic computing to shorten time to tapeout by 2x.
Learn how to use IC Validator on the cloud to run DRC checking, scaling for faster performance, and Elastic CPU Management to add and remove CPUs on the fly.
Learn how to use Explorer DRC for super-fast design verification during SoC integration. Explorer enables designers to run DRC faster and isolate gross design weaknesses within hours instead of days.
Barefoot Networks: IC Validator Physical Signoff on AWS Cloud
Nvidia: IC Validator for Physical Signoff of Full-Reticle GPU Designs
Learn about Toshiba’s experience using IC Validator physical signoff on ADAS chips. Toshiba achieves overnight full chip signoff and accelerates physical verification closure to less than a week.
Learn about Barefoot Networks’ experience about using IC Validator physical signoff on Amazon Web Services Cloud. IC Validator scaling on the cloud delivers full chip DRC signoff within a day and 2-day runtime savings.
2020欧洲杯体育投注网Nvidia shares their experience with IC Validator. Increased design complexity and large designs are putting pressure on designers to deliver tapeouts on-time.